Pascal Sasdrich

Biography #

© Nordrhein-Westfälische Akademie der Wissenschaften und der Künste |
Bettina Engel-Albustin 2023 (NRW AWK| Engel-Albustin)

I am head of the research group on Computer-Aided Verification of Physical Security Properties (CAVE) hosted at the Faculty of Computer Science, Ruhr University Bochum, Germany. My group is funded by the Deutsche Forschungsgemeinschaft (DFG, German Research Foundation) as part of the Emmy Noether Programme. In addition, I am a Principal Investigator (PI) at the Cluster of Excellence CASA – Securing the Digital Society.

Before, I worked as a Senior Hardware Security Engineer at the Rambus Cryptography Research Group located in Rotterdam, The Netherlands. I obtained my PhD (Dr.-Ing.) in 2018 on the topic of Cryptographic Hardware Agility for Physical Protection under the supervision of Prof. Dr.-Ing. Tim Güneysu at the Ruhr University Bochum, Germany.

My current research focuses on Hardware Security and Computer-Aided Security Engineering. For this, I work on new concepts and approaches for Hardware Security Verification and Security-Oriented Electronic Design Automation to enable efficient and automated protection of hardware implementations through sophisticated and specialized security-aware design and verification tools.

Curriculum Vitae #

Head of the Emmy Noether Research Group CAVE at the Faculty of Computer Science, Ruhr University Bochum, Germany. The group on Computer-Aided Verification of Physical Security Properties is funded by the Deutsche Forschungsgemeinschaft (DFG).

Akademischer Rat at the Chair for Security Engineering, Faculty of Computer Science, Ruhr University Bochum, Germany (permanent civil-servant position since May 2023).

Postdoctoral Researcher at the Chair for Security Engineering, Faculty of Computer Science, Ruhr University Bochum, Germany.

Senior Hardware Security Engineer at Rambus Inc., Rotterdam, The Netherlands. Research and development in hardware security (side-channel resistance, hardware root of trust) and automotive functional safety (ISO 26262).

Cryptography Engineering Intern at Rambus Inc., San Francisco, USA. Research and development in hardware security (side-channel resistance).

Dr.-Ing. (PhD) in Electrical Engineering and Information Technology at Ruhr University Bochum, Germany, working as a research assistant in the Secure Hardware group, the Chair for Embedded Security, and the Chair for Security Engineering. Thesis: Cryptographic Hardware Agility for Physical Protection.

M.Sc. in IT Security / Information Technology at Ruhr University Bochum, Germany.

B.Sc. in IT Security / Information Technology at Ruhr University Bochum, Germany.

Honors and Awards #

Principal Investigator (PI) at the Cluster of Excellence for CASA – Securing the Digital Society at the Ruhr University Bochum (RUB).link

Admission to the Young College of the Nordrhein-Westfälische Akademie der Wissenschaften und der Künste.link

Associate Principal Investigator (PI) at the Cluster of Excellence for Cyber Security in the Age of Large Scale Adversaries (CASA) at the Ruhr University Bochum (RUB).link

German IT Security Prize (100.000 €) (1st place of the 9th German IT Security Prize) awarded by the Horst Görtz Stiftung for the toolbox Einfach sicher: Ein Werkzeugkasten zur automatisierten Erstellung geschützter Hardware, together with David Knichel, Amir Moradi and Nicolai Müller.link

News #

CHARRM (preprint). Preprint CHARRM: Characterizing Hardware Leakage in the Robust Random Probing Model with Armand Schinkel on the IACR ePrint Archive.

OPTIMIST 2026 (PC Member). Program Committee member of the OPTIMIST 2026 workshop.

CHES 2027 (PC Member). Program Committee member of the CHES 2027 conference.

FDTC 2026 (PC Member). Program Committee member of the FDTC 2026 conference.

ASIACRYPT 2026 (PC Member). Program Committee member of the Asiacrypt 2026 conference.

EUROCRYPT 2026 (accepted paper). Paper PaCMan – Partition-Code Masking for Combined Security at Eurocrypt 2026.

Implementing Cryptographic Schemes (Course). 30-hours Master’s course on Implementing Cryptographic Schemes at the African Institute of Mathematical Sciences (AIMS) in Limbe, Cameroon.

TCHES 2026.2 (accepted paper). Paper Combined Indistinguishability Analysis - Verifying random probing leakage under random faults at CHES 2026 (published in TCHES 2026, Issue 2).

CHES 2026 (Artifact Evaluation Committee Co-Chair). Artifact Evaluation Committee Co-Chair of the CHES 2026 conference, together with Ileana Buhan.

CyBARsecurity (science slam). Science slam on Seitenkanalangriffe - Wenn Hacker zwischen den Zeilen lesen at the CyBARsecurity event in Bochum (presentation in German only).

Eurocrypt 2025 (research talk). Research talk on INDIANA - Verifying (Random) Probing Security through Indistinguishability Analysis at Eurocrypt 2025.

PROACT Training School 2025 (invited talk). Invited talk on Automated Verification of Physical Security Properties at the PROACT Training School.

FDTC 2025 (PC Member). Program Committee member of the FDTC 2025 conference.

ASIACRYPT 2025 (PC Member). Program Committee member of the Asiacrypt 2025 conference.

EUROCRYPT 2025 (accepted paper). Paper INDIANA - Verifying (Random) Probing Security through Indistinguishability Analysis at Eurocrypt 2025.

Research #

Research Group #

The research group Computer-Aided Verification of Physical Security Properties (CAVE) is an Emmy Noether group funded by the Deutsche Forschungsgemeinschaft (DFG) since 2023 and hosted at the Faculty of Computer Science, Ruhr University Bochum. The group develops formal models of physical attackers and automated methods and tools to verify the security of hardware implementations against side-channel and fault-injection attacks, and to build protected systems based on them.

Supervised PhD Students #

Felix Raback (CAVE, Ruhr University Bochum). First supervisor.

Khan Keren Mengwi (University of Bamenda, Cameroon). Co-supervisor (first supervisor: Emmanuel Fouotsa).

Ting-Yun Yeh (CAVE, Ruhr University Bochum). First supervisor.

Armand Schinkel (CAVE, Ruhr University Bochum). First supervisor.

Jakob Feldtkeller (Chair for Security Engineering, Ruhr University Bochum). Scientific supervisor (first supervisor: Tim Güneysu).

Jan Richter-Brockmann (Chair for Security Engineering, Ruhr University Bochum). Scientific supervisor (first supervisor: Tim Güneysu).

Third-Party Funded Projects #

EASEPROFIT Agile and Post-Quantum-Secure Protocols for the Finance Industry. BMFTR joint project in the programme Bringing Post-Quantum Cryptography into Applications (joint proposal with Tim Güneysu).

DI-OWAS Open Tools for Adaptive SoCs with AI and Cryptography. BMFTR joint project in the programme Design Tools for Sovereign Chip Development with Open Source (joint proposal with Tim Güneysu).

DI-OCDCpro Open-Source Chip Design Infrastructure as a Learning and Competition Platform for Students and Young Talents. BMFTR joint project in the programme Design Tools for Sovereign Chip Development with Open Source (joint proposal with Tim Güneysu).

EMBOSOM Security of Embedded Software through Modern Emerging Hardware Paradigms. DFG Priority Programme Nano Security (joint proposal with Rolf Drechsler, Christoph Lüth and Tim Güneysu).

CAVE Computer-Aided Verification of Physical Security Properties. DFG Emmy Noether Programme.link

CONVOLVE Seamless design of smart edge processors. EU Research and Innovation Action Ultra-low-power, secure processors for edge computing (joint proposal with Tim Güneysu).

PROVECTA Processor Verification for Combined Threats and Attacks. Industry-funded project in the programme Secure Processor Assurance and Resilience (SPAR) (joint proposal with Tim Güneysu).

VE-HEP Hardening of the Value Chain through Open-Source, Trustworthy EDA Tools and Processors. BMFTR joint project in the programme Trustworthy Electronics (joint proposal with Tim Güneysu).

Software and Tools #

INDIANA. Verification of masked hardware against more complex passive attacker models, including random probing leakage, based on indistinguishability analysis. repository

HADES. Automated design space exploration for protected implementations of cryptographic primitives, trading off security, area and latency. repository

VERICA. Formal verification of circuits against combined attacks, i.e., simultaneous information leakage (side channels) and tampering (fault injection). repository

AGEMA. Automated generation of masked, side-channel-resistant hardware from unprotected gate-level netlists. repository

FIVER. Robust formal verification of countermeasures against active physical attacks (fault-injection analysis). repository

SILVER. Statistical independence and leakage verification: formal verification of masked circuits against passive physical attacks (side-channel analysis). repository

Publications #

Journal Articles #

Combined Indistinguishability Analysis - Verifying random probing leakage under random faults. Armand Schinkel and Pascal Sasdrich. IACR Transactions on Cryptographic Hardware and Embedded Systems Issue 2 (2026) code doi paper preprint

HADES: Automated Hardware Design Exploration for Cryptographic Primitives. Fabian Buschkowski, Georg Land, Niklas Höher, Jan Richter-Brockmann, Pascal Sasdrich and Tim Güneysu. IACR Transactions on Cryptographic Hardware and Embedded Systems Issue 4 (2025) code doi paper preprint slides

Multivariate TVLA - Efficient Side-Channel Evaluation Using Confidence Intervals. Florian Bache, Jonas Wloka, Pascal Sasdrich and Tim Güneysu. IEEE Transactions on Computers 74.3 (2025) doi

Combined Threshold Implementation. Jakob Feldtkeller, Jan Richter-Brockmann, Pascal Sasdrich and Tim Güneysu. IACR Transactions on Cryptographic Hardware and Embedded Systems Issue 4 (2024) doi paper preprint

Challenges and Opportunities of Security-Aware EDA. Jakob Feldtkeller, Pascal Sasdrich and Tim Güneysu. ACM Transactions on Embedded Computing Systems 22.3 (2023) doi paper

Revisiting Fault Adversary Models - Hardware Faults in Theory and Practice. Jan Richter-Brockmann, Pascal Sasdrich and Tim Güneysu. IEEE Transactions on Computers 72.2 (2023) doi preprint

Risky Translations: Securing TLBs against Timing Side Channels. Florian Stolz, Jan Philipp Thoma, Pascal Sasdrich and Tim Güneysu. IACR Transactions on Cryptographic Hardware and Embedded Systems Issue 1 (2023) doi paper preprint slides

VERICA - Verification of Combined Attacks. Automated Formal Verification of Security against Simultaneous Information Leakage and Tampering. Jan Richter-Brockmann, Jakob Feldtkeller, Pascal Sasdrich and Tim Güneysu. IACR Transactions on Cryptographic Hardware and Embedded Systems Issue 4 (2023) artifacts code doi paper preprint slides

Randomness Optimization for Gadget Compositions in Higher-Order Masking. Jakob Feldtkeller, David Knichel, Pascal Sasdrich, Amir Moradi and Tim Güneysu. IACR Transactions on Cryptographic Hardware and Embedded Systems Issue 4 (2022) code doi paper preprint slides

Transitional Leakage in Theory and Practice. Unveiling Security Flaws in Masked Circuits. Nicolai Müller, David Knichel, Pascal Sasdrich and Amir Moradi. IACR Transactions on Cryptographic Hardware and Embedded Systems Issue 2 (2022) code doi paper preprint slides

Generic Hardware Private Circuits. Towards Automated Generation of Composable Secure Gadgets. David Knichel, Pascal Sasdrich and Amir Moradi. IACR Transactions on Cryptographic Hardware and Embedded Systems Issue 1 (2022) code doi paper preprint slides

Automated Generation of Masked Hardware. David Knichel, Amir Moradi, Nicolai Müller and Pascal Sasdrich. IACR Transactions on Cryptographic Hardware and Embedded Systems Issue 1 (2022) code doi paper preprint slides

FIVER - Robust Verification of Countermeasures against Fault Injections. Jan Richter-Brockmann, Aein Rezaei Shahmirzadi, Pascal Sasdrich, Amir Moradi and Tim Güneysu. IACR Transactions on Cryptographic Hardware and Embedded Systems Issue 4 (2021) artifacts code doi paper preprint video

SKINNY-AEAD and SKINNY-Hash. Christof Beierle, Jérémy Jean, Stefan Kölbl, Gregor Leander, Amir Moradi, Thomas Peyrin, Yu Sasaki, Pascal Sasdrich and Siang Meng Sim. IACR Transactions on Symmetric Cryptology Issue 1 (2020) doi paper video

Low-Latency Hardware Masking with Application to AES. Pascal Sasdrich, Begül Bilgin, Michael Hutter and Mark E. Marson. IACR Transactions on Cryptographic Hardware and Embedded Systems Issue 2 (2020) doi paper video

Exploring RFC 7748 for Hardware Implementation: Curve25519 and Curve448 with Side-Channel Protection. Pascal Sasdrich and Tim Güneysu. Journal of Hardware and Systems Security 2.4 (2018) doi paper

Implementing Curve25519 for Side-Channel-Protected Elliptic Curve Cryptography. Pascal Sasdrich and Tim Güneysu. ACM Transactions on Reconfigurable Technology and Systems 9.1 (2015) doi paper

Conference and Workshop Papers #

PaCMan – Partition-Code Masking for Combined Security. Fabian Buschkowski, Elisabeth Krahmer, Jakob Feldtkeller, Jan Richter-Brockmann, Pascal Sasdrich and Tim Güneysu. Annual International Conference on the Theory and Applications of Cryptographic Techniques (2026) doi preprint

INDIANA - Verifying (Random) Probing Security through Indistinguishability Analysis. Christof Beierle, Jakob Feldtkeller, Anna Guinet, Tim Günyesu, Gregor Leander, Jan Richter-Brockmann and Pascal Sasdrich. Annual International Conference on the Theory and Applications of Cryptographic Techniques (2025) artifacts code doi paper preprint video

Formal Definition and Verification for Combined Random Fault and Random Probing Security. Sonia Belaid, Jakob Feldtkeller, Tim Güneysu, Anna Guinet, Jan Richter-Brockmann, Matthieu Rivain, Pascal Sasdrich and Abdul Rahman Taleb. Advances in Cryptology (2024) doi paper preprint slides

Evaluating an Open-Source Hardware Approach from HDL to GDS for a Security Chip Design - a Review of the Final Stage of Project HEP. Tim Henkes, Steffen Reith, Marc Stöttinger, Norbert Herfurth, Goran Panic, Julian Wälde, Fabian Buschkowski, Pascal Sasdrich, Christoph Lüth, Milan Funck, Tuba Kiyan, Arnd Weber, Detlef Boeck, René Rathfelder and Torsten Grawunder. Design, Automation & Test in Europe (2024) doi

Combined Private Circuits - Combined Security Refurbished. Jakob Feldtkeller, Tim Güneysu, Thorben Moos, Jan Richter-Brockmann, Sayandeep Saha, Pascal Sasdrich and Francois-Xavier Standaert. Computer and Communications Security (2023) doi paper preprint

EasiMask - Towards Efficient, Automated, and Secure Implementation of Masking in Hardware. Fabian Buschkowski, Pascal Sasdrich and Tim Güneysu. Design, Automation & Test in Europe (2023) doi paper

Recommendation for a Holistic Secure Embedded ISA Extension. Florian Stolz, Marc Fyrbiak, Pascal Sasdrich and Tim Güneysu. Applied Cryptography and Network Security (2023) doi paper

CINI MINIS: Domain Isolation for Fault and Combined Security. Jakob Feldtkeller, Jan Richter-Brockmann, Pascal Sasdrich and Tim Güneysu. Computer and Communications Security (2022) doi paper preprint

A Hard Crystal - Implementing Dilithium on Reconfigurable Hardware. Georg Land, Pascal Sasdrich and Tim Güneysu. Smart Card Research and Advanced Applications (2021) doi paper preprint

SILVER - Statistical Independence and Leakage Verification. David Knichel, Pascal Sasdrich and Amir Moradi. Advances in Cryptology (2020) code doi paper preprint slides video

Concurrent Error Detection Revisited: Hardware Protection against Fault and Side-Channel Attacks. Jan Richter-Brockmann, Florian Bache, Pascal Sasdrich and Tim Güneysu. Availability, Reliability and Security (2020) doi paper

Protecting Triple-DES Against DPA - A Practical Application of Domain-Oriented Masking. Pascal Sasdrich and Michael Hutter. Constructive Side-Channel Analysis and Secure Design (2018) doi paper

Threshold Implementation in Software - Case Study of PRESENT. Pascal Sasdrich, René Bock and Amir Moradi. Constructive Side-Channel Analysis and Secure Design (2018) doi paper preprint

Bit-Sliding: A Generic Technique for Bit-Serial Implementations of SPN-based Primitives - Applications to AES, PRESENT and SKINNY. Jérémy Jean, Amir Moradi, Thomas Peyrin and Pascal Sasdrich. Cryptographic Hardware and Embedded Systems (2017) doi paper preprint

Cryptography for Next Generation TLS: Implementing the RFC 7748 Elliptic Curve448 Cryptosystem in Hardware. Pascal Sasdrich and Tim Güneysu. Design Automation Conference (2017) doi paper preprint

Hiding Higher-Order Side-Channel Leakage - Randomizing Cryptographic Implementations in Reconfigurable Hardware. Pascal Sasdrich, Amir Moradi and Tim Güneysu. Cryptographers' Track at the RSA Conference (2017) doi paper preprint

A grain in the silicon: SCA-protected AES in less than 30 slices. Pascal Sasdrich and Tim Güneysu. Application-specific Systems, Architectures and Processors (2016) doi paper

The SKINNY Family of Block Ciphers and Its Low-Latency Variant MANTIS. Christof Beierle, Jérémy Jean, Stefan Kölbl, Gregor Leander, Amir Moradi, Thomas Peyrin, Yu Sasaki, Pascal Sasdrich and Siang Meng Sim. Advances in Cryptology (2016) doi paper preprint

White-Box Cryptography in the Gray Box - A Hardware Implementation and its Side Channels. Pascal Sasdrich, Amir Moradi and Tim Güneysu. Fast Software Encryption (2016) doi paper preprint

Affine Equivalence and Its Application to Tightening Threshold Implementations. Pascal Sasdrich, Amir Moradi and Tim Güneysu. Selected Areas in Cryptography (2015) doi paper preprint

Side-Channel Protection by Randomizing Look-Up Tables on Reconfigurable Hardware - Pitfalls of Memory Primitives. Pascal Sasdrich, Oliver Mischke, Amir Moradi and Tim Güneysu. Constructive Side-Channel Analysis and Secure Design (2015) doi paper preprint

Achieving side-channel protection with dynamic logic reconfiguration on modern FPGAs. Pascal Sasdrich, Amir Moradi, Oliver Mischke and Tim Güneysu. Hardware Oriented Security and Trust (2015) doi paper preprint

THOR - The hardware onion router. Tim Güneysu, Francesco Regazzoni, Pascal Sasdrich and Marcin Wójcik. Field Programmable Logic and Applications (2014) doi paper

Efficient Elliptic-Curve Cryptography Using Curve25519 on Reconfigurable Devices. Pascal Sasdrich and Tim Güneysu. Reconfigurable Computing: Architectures, Tools, and Applications (2014) doi paper

Preprints and Technical Reports #

CHARRM: Characterizing Hardware Leakage in the Robust Random Probing Model. Armand Schinkel and Pascal Sasdrich. IACR Cryptology ePrint Archive (2026) preprint

A Billion Hard CRYSTALS: Exploring Practical Aspects of Arithmetic Masking for PQC in Hardware. Fabian Buschkowski, Niklas Höher, Pascal Sasdrich and Tim Güneysu. IACR Cryptology ePrint Archive (2026) preprint

Talks #

Invited Talks #

Automated Verification of Physical Security Properties, PROACT Training School, 2025, Samaria Hotel, Chania, Crete, Greeceslides

Computer-Aided Hardware Security Verification, VeriSiCC Seminar, 2022, Paris, Franceslides

Statistical Independence and Leakage Verification (SILVER), ISC Winter School on Information Security, 2021, Virtual, Earthslides

Implementing Curve25519 for Side-Channel-Protected Elliptic Curve Cryptography, Workshop on Elliptic Curve Cryptography, 2016, Izmir, Turkeyslides

Conference and Workshop Talks #

INDIANA - Verifying (Random) Probing Security through Indistinguishability Analysis, Annual International Conference on the Theory and Applications of Cryptographic Techniques, 2025, Madrid, Spainslides

Low-Latency Hardware Masking with Application to AES, Cryptographic Hardware and Embedded Systems, 2020, Virtual, Earthslides

Threshold Implementation in Software - Case Study of PRESENT, Constructive Side-Channel Analysis and Secure Design, 2018, Singapore

Protecting Triple-DES Against DPA - A Practical Application of Domain-Oriented Masking, Constructive Side-Channel Analysis and Secure Design, 2018, Singapore

Hiding Higher-Order Side-Channel Leakage - Randomizing Cryptographic Implementations in Reconfigurable Hardware, Cryptographers' Track at the RSA Conference, 2017, San Francisco, California, USAslides

Hiding Higher-Order Side-Channel Leakage - Randomizing Threshold Implementations in Reconfigurable Hardware, Trustworthy Manufacturing and Utilization of Secure Devices, 2016, Barcelona, Spainslides

A Grain in the Silicon: SCA-Protected AES in Less Than 30 Slices, Application-specific Systems, Architectures and Processors, 2016, Imperial College London, London, Englandslides

White-Box Cryptography in the Gray Box - A Hardware Implementation and its Side Channels, Fast Software Encryption, 2016, Bochum, Germanyslides

Pushing the Limits: Ultra-Lightweight AES on Reconfigurable Hardware, Trustworthy Manufacturing and Utilization of Secure Devices, 2015, Saint-Malo, Franceslides

Side-Channel Protection with Dynamic Logic Reconfiguration and Randomized Look-Up Tables on FPGAs, Selected Areas in Cryptography, 2015, Mount Allison University, Sackville, New Brunswick, Canadaslides

Side-Channel Protection with Dynamic Logic Reconfiguration and Randomized Look-Up Tables on FPGAs, Krypto-Tag, 2015, Infineon Technologies AG, Munich, Germanyslides

Achieving Side-Channel Protection with Dynamic Logic Reconfiguration on Modern FPGAs, Hardware Oriented Security and Trust, 2015, McLean, Virgina, USAslides

Side-Channel Protection by Randomizing Look-Up Tables on Reconfigurable Hardware - Pitfalls of Memory Primitives, Constructive Side-Channel Analysis and Secure Design, 2015, Berlin, Germanyslides

Efficient Elliptic-Curve Cryptography using Curve25519 on Reconfigurable Devices, Krypto-Tag, 2014, T-Labs, Berlin, Germanyslides

Efficient Elliptic-Curve Cryptography using Curve25519 on Reconfigurable Devices, Reconfigurable Computing: Architectures, Tools, and Applications, 2014, Vilamoura, Algarve, Portugalslides