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Combined Threshold Implementation
Jakob Feldtkeller, Jan Richter-Brockmann, Pascal Sasdrich, Tim Güneysu
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INDIANA - Verifying (Random) Probing Security through Indistinguishability Analysis
Christof Beierle, Jakob Feldtkeller, Anna Guinet, Tim Güneysu, Gregor Leander, Jan Richter-Brockmann, Pascal Sasdrich
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Challenges and Opportunities of Security-Aware EDA
Jakob Feldtkeller, Pascal Sasdrich, Tim Güneysu
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Revisiting Fault Adversary Models - Hardware Faults in Theory and Practice
Jan Richter-Brockmann, Pascal Sasdrich, Tim Güneysu
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Risky Translations: Securing TLBs against Timing Side Channels
Florian Stolz, Jan Philipp Thoma, Pascal Sasdrich, Tim Güneysu
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Automated Generation of Masked Hardware
David Knichel, Amir Moradi, Nicolai Müller, Pascal Sasdrich
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Generic Hardware Private Circuits Towards Automated Generation of Composable Secure Gadgets
David Knichel, Pascal Sasdrich, Amir Moradi
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Randomness Optimization for Gadget Compositions in Higher-Order Masking
Jakob Feldtkeller, David Knichel, Pascal Sasdrich, Amir Moradi, Tim Güneysu
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Transitional Leakage in Theory and Practice Unveiling Security Flaws in Masked Circuits
Nicolai Müller, David Knichel, Pascal Sasdrich, Amir Moradi
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VERICA - Verification of Combined Attacks Automated formal verification of security against simultaneous information leakage and tampering
Jan Richter-Brockmann, Jakob Feldtkeller, Pascal Sasdrich, Tim Güneysu
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